1. Field of the invention
The present invention relates to a focus detecting device for use, for example, in a camera, and provided with a self-scanning type image sensor having an image sensor array defined by a charge accumulation portion and charge transfer portion for transferring the accumulated charge.
2. Description of the Prior Art
A self-scanning type image sensor is known in the prior art, and is defined by a CCD (Charge Coupled Device) having a photodiode array serving as a charge accumulation portion and a CCD shift register serving as a charge transfer portion. When a positive going pulse, which is generally called an integration clear pulse, is applied to the CCD, all the photodiodes in the photodiode array are once charged up to the level approximately equal to the voltage of power source. Then, when the integration clear pulse disappears, the discharge starts at a speed relative to the intensity of light impinging on each photodiode. Since such a discharge can be regarded as a negative charge, it is referred to as "an accumulation of charge" in the description herein. Then, when the next positive going pulse, which is generally called a shift pulse, is applied to the CCD, the accumulated charge in each photodiode is transferred to a corresponding cell in the charge transfer portion. Then, in accordance with the transfer clock pulses, the charge stored in the transfer portion is sequentially transferred to an image signal output circuit. From the image signal output circuit, the accumulated charge, which is changed to a voltage signal, is produced. Then, the voltage signal is converted to a digital signal for being processed in a processor through a certain program, thereby producing a signal representing the focus condition of the image formed on the photodiode array.
According to the above described image sensor, it is necessary to control the time when to produce the shift pulse with respect to the brightness of the aiming object. Otherwise, if the shift pulse is produced always with the same time interval from the start of the charge accumulation, the accumulated charge will be very low when the object is very dark and, on the contrary, the accumulated charge in each photodiode will saturate when the object is very bright. In either one of the above cases, the obtained image signal becomes very poor. Accordingly, it is necessary to provide a means for varying the time when to produce the shift pulse in accordance with the brightness of the object. Such a varying means includes a monitor light receiving means, a monitoring circuit for producing a voltage signal varying at a speed dependent on the brightness of the object detected by the monitor light receiving means, and a comparing means for comparing the voltage signal from the monitoring circuit with a reference voltage. When the integration clear pulse disappears, the voltage signal from the monitoring circuit gradually decreases at a speed dependent on the brightness of the object detected by the monitor light receiving means. The voltage signal is compared with the reference voltage in the comparing means, and when the voltage signal is reduced to a level equal to the reference voltage, the shift pulse is generated.
In the above described arrangement, the problem is the reliability of the reference voltage, as explained below.
Upon disappearance of the integration clear pulse, the voltage signal from the monitor circuit starts to drop at a speed determined by the brightness of the object. Also, the voltage signal which has been produced before the generation of the integration clear pulse is variable depending on the brightness of the object and other factors. Accordingly, it is very difficult to obtain the reference voltage from the output of the monitoring circuit itself.
To solve the problem, the reference voltage may be supplied from a constant voltage source. However, when the voltage from a power source, supplying power to the monitoring circuit, varies, the initial voltage of the voltage signal produced upon disappearance of the integration clear pulse varies. Accordingly, the result of the comparison will also become poor when the reference voltage is constant regardless of various environmental changes, but if the voltage signal varies not only by the change in the brightness of the object, but also by the other environmental changes, such as a temperature change. Accordingly, it may happen such that, while aiming at the same object, the timing of generation of the shift pulse may change relative to the temperature change.
Another approach to solve the problem is to generate the reference voltage using the same power source as that for the monitoring circuit, but the problem still remains. More specifically, the change in the voltage signal by the environmental change is partly dependent on the monitoring circuit itself, and also the power source produces much noise signal which is not preferable for the reference voltage.
Furthermore, the shift pulse should be generated relatively to the transfer-clock pulses. Generally, a selfscanning type image sensor, such as a CCD, requires at least two sets of clock pulses of different phases for the transfer of the accumulated charge. The charge in each cell is transferred in response to the step-down of the transfer-clock pulse of a particular phase. Accordingly, the shift pulse should be produced while the transfer-clock pulse is still in HIGH (stepped up) state. Conventionally, since the transfer-clock pulse is always produced at a given frequency, the generation of the shift pulse is delayed until the transfer-clock pulse changes its state to HIGH, in the case when the comparing means detects that the voltage signal is reduced to a level equal to the reference voltage, during the clock pulse in LOW state. Such a delay in the generation of the shift pulse undesirably extends the charging period, thereby saturating the charge in each photodiode, particularly when the aiming object is bright.
Also, conventionally, the photodiode array starts to accumulate charge after completing the previous cycle of focus detection, i.e., after processing the image signal in the processor through a certain program. In other words, the integration clear pulse is produced always after the completion of the image signal processing in the processor. Since the speed of charge accumulation in the photodiode array is in relation to the brightness of the object, it is necessary to continue the charge accumulation for a relatively long period of time when a dark object is aimed, eventually resulting in the prolongation of one focus detection cycle. Thus, the number of focus detection cycles which can be carried out in a certain period of time will be reduced. When the focus detecting device of the above described type is employed in a camera which automatically moves the objective lens in succession in accordance with the signal representing the detected focus condition with the focus condition detection repeated, it will take a relatively long time before the lens is moved to the proper focusing position, thereby losing a good picture shooting chance.
In addition, since at least two sets of clock pulses of different phases for the transfer of the accumulated charge are necessary, the duty cycle of the clock pulse in each phase is usually defined as 50% in conventional focus detecting devices using CCD. Since the voltage signal representing the charge in each cell is transferred in response to the step-down of the transfer-clock pulse of a particular phase, and since the noise signals will be produced at the step-up of the transfer-clock pulse, it is necessary to complete the A/D conversion of the voltage signal from the image signal output circuit in a time interval between the step-down of the pulse and the step-up of the subsequent pulse. Since the time interval between the subsequent pulses is very short, particularly with the 50% duty cycle, it is necessary to provide a high speed A/D converter, which is very expensive, resulting in the high manufacturing cost of the camera. A sample-hold circuit may be employed to temporarily hold the voltage signal for use in combination with a moderate speed A/D converter. However, such a sample-hold circuit requires a capacitor, which must be connected externally of the chip carrying various electronic elements, resulting in bulky in size and high manufacturing cost.
There are still other problems in conventional focus detecting devices using the self-scanning type image sensor. When the power switch is turned on, unwanted charges are accumulated in the photodiode array which must be cleared away before the first detecting operation, or otherwise the signal obtained from the first detecting operation will not carry the correct image signal. Accordingly, the objective lens will not be moved to the proper focusing position. To this end, an initialize operation is carried out after the turn on of an operation start switch. The initialize operation is carried out by a so-called trial or idle transfer operation in which the unwanted charges are transferred from the photodiode array through the CCD shift register to the image signal output circuit, for example, with the signal produced by the image signal output circuit not used. Usually, to completely remove the unwanted charges, the trial transfer operation is carried out for a several times repeatedly. Since such a trial transfer operation is carried out at the same speed as the normal transfer operation which can not be made faster due to the various factors, such as the speed of the A/D conversion, it takes time before the camera is ready to take a first picture. Thus, one may lose a good picture shooting chance in this respect also.
Even if the trial transfer operation can be made faster than the normal transfer operation, the problem still exists as explained below.
It is to be noted that the CCD shift register itself is sensitive to light, such that the charge in each cell of the CCD shift register increases, although very slowly, but, relatively to the light impinging thereon. It is assumed that the CCD shift register is disconnected from the photodiode array in the trial transfer operation and comprises seven cells aligned in a row. It is also assumed that the fast trial operation is carried out by fast transfer-clock pulses having a high frequency fH, which is higher than the frequency fL of the normal transfer-clock pulse for the normal transfer operation.
Now description is given to the last trial transfer operation. At the moment of the completion of the next to the last trial transfer operation, there are accumulated unwanted charges "6q", "5q", "4q", "3q", "2q" and "q" in the first to sixth cells, respectively, and the seventh cell is empty. Until the first fast transfer-clock pulse for the last trial transfer operation is produced, that is for a period 1/fH, each cell accumulates unwanted charge "q". When the first fast transfer-clock pulse for the last trial transfer operation is produced, unwanted charge "7q" in the first cell in the CCD shift register is outputed from the CCD shift register, unwanted charge "6q" in the second cell is moved to the first cell, unwanted charge "5q" in the third cell is moved to the second cell, and in this manner, unwanted charge in the last seventh cell "q" is moved to the sixth cell.
Until the second fast transfer-clock pulse is produced, that is for a period 1/fH, each cell further accumulates unwanted charge "q". Then, when the second fast transfer-clock pulse is produced, the same brigade operation is carried out.
In this manner, the last trial transfer operation completes when the seventh fast transfer-clock pulse is produced. When the seventh fast transfer-clock pulse is produced, the first cell receives unwanted charge "6q", the second cell receives unwanted charge "5q", and in this manner, the sixth cell receives unwanted charge "q" while the seventh cell becomes empty and the CCD register starts to accumulate unwanted charges from the beginning.
After the last trial transfer operation, the normal transfer operation starts using the normal transfer-clock pulse.
Until the first normal transfer-clock pulse is produced, that is for a period 1/fL, each cell further accumulates unwanted charge "Q" which is a greater than the charge "q". When the first normal transfer-clock pulse is produced, the unwanted charge in the first cell, which is now equal to "6q+Q", is outputed from the CCD shift register. Similarly, unwanted charge "5q+Q" in the second cell is moved to the first cell, unwanted charge "4q+Q" in the third cell is moved to the second cell, and in this manner, unwanted charge "Q" in the last seventh cell is moved to the sixth cell.
Then, when the second normal transfer-pulse is produced, the first cell outputs unwanted charge "5q+2Q". Then, when the third normal transfer-pulse is produced, the first cell outputs unwanted charge "4q+3Q". In this manner, until the seventh normal transfer-pulse, the unwanted charge outputed from the CCD shift register changes "6q+Q", "5q+2Q", "4q+3Q", "3q+4Q", "2q+5Q", "1q+6Q"and "7Q". Thus, in the first cycle of the normal transfer operation, the unwanted charge is not constant but varies increasingly, thereby causing an error in the focus detection.